1. Field of the Invention
The field of the invention relates to the field of data processing and in particular, to reducing power consumption in data processing circuitry by gating the clock signal supplied to portions of the circuitry when they are not active.
2. Description of the Prior Art
In many circuits, particularly those that run off remote power supplies such as batteries, it is important to keep the power consumption of the circuits low. One way of doing this has been to gate the clock signal supplied to synchronous elements when they are not operational. The clock signal consumes a lot of power in a circuit and thus, being able to gate it in certain parts of the circuit that do not require it can save a significant amount of power.
In modem circuits a clock signal is often supplied to several synchronous elements via a clock gating cell. These cells are controlled by their own clock enable signal and in response to this either supply the clock signal to the synchronous elements or gate the clock signal. In this way the synchronous elements can either be clocked or not and power can be saved.
A further way of saving power is to provide a circuit with a sleep mode so that it is in effect powered down during non-operational periods.
Although this results in substantial power savings it also results in a loss of state within the circuitry. If it is desired that the circuit retain state during sleep mode, data retention circuits such as special data retention flip-flops must be used within the design. Such a mode of operation allows the stored signal values to be securely held in a small portion of the circuitry whilst the remainder of the circuitry is powered down for leakage reduction purposes. When power is resumed, the saved signal value is restored and operation continues. One approach to supporting data retention in this way is to add balloon latches to the flip-flops such that signal values can be transferred into the balloon latches which have their own power supply, and then the power supply removed from the remainder of the flip-flops. A disadvantage of this approach is that the balloon latches consume considerable additional circuit area.
Other designs have used master slave flip flops where the slave is powered during sleep mode and retains the state while the master is powered down. In order to avoid the slave losing state the transmission gate between the master and slave must be in the isolated or closed state for the whole period that the master is powered down. This requires a control signal to be sent to each transmission gate and has significant routing overheads.
It would be desirable to be able to reduce power consumption while retaining state without undue area or signal routing overheads.